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Verification Engineer

-Should have worked on ASIC Verification on at least one project with constrained -Domain : OVM, Low Power Verification, System Verilog, Verilog, VHDL etc Scripting : Perl, Makefile, C, mySQL, database design Project Experience : Folks who have worked on the ASIC Design Verification flow like Verifying IP s, Soc s, creation of testbenches, creation of verification environments, -Writing testplans etc. Education required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering Preferred: Master's, Computer Engineering and/or Computer Science Experience level : 2 to 8 years