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Physical Design Engineer- Onsite at US

Skills: Floor Planning, Timing Closure, Soc Encounter, Routing, Physical Design Experience: 4-7 years Education: BE/ Btech The company will process H1 Visa to fly to USA Interested candidates mail your updated resume to betsy@roljobs.com with current ctc and expected ctc.

  • Date Posted:  17-Aug-2012
  • Experience Level:  4 to 7 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area:  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  United States
  • Salary:  100000 - 2000000
  • Job Type:  Permanent

Keywords:Floor planning Physical Design Routing Soc encounter

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100% Match

Physical Design Engineer- Onsite at US

Skills: Floor Planning, Timing Closure, Soc Encounter, Routing, Physical Design Experience: 4-7 years Education: BE/ Btech The company will process H1 Visa to fly to USA Interested candidates mail your updated resume to anjali@roljobs.com with current ctc and expected ctc.

  • Date Posted:  17-Aug-2012
  • Experience Level:  4 to 7 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area:  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  United States
  • Salary:  100000 - 2000000
  • Job Type:  Permanent

Keywords:Floor planning Physical Design Routing Soc encounter

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100% Match

Physical design Engineer Jobs with 20+ Lakhs Salary

Position : Physical designExperience : 3- 9 yearsLocation : BangaloreQualification : B.E. / B.Tech / M.E. / M.TechDescription :·Successful implementation of multimillion gate SoC designs in 65nm,45nm,28nm technologies·Should be capable of handling block of 1M plus place able instances·Hands on experience in complete Netlist to GDS implementation on high frequency design·Hands-On expertise in flip-chip designs·Work on all aspects of physical design including synthesis, IO ring creation, Bump placement , floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tape out·Expertise in executing hierarchical designs - Floor planning, Partitioning, Budgeting, Integration and Signoff·Expertise in Signoff - STA with Crosstalk and OCV, IR - Static and Dynamic, Physical Verification Closure.·Low Power expertise - UPF/CPF based Floor planning and Optimization·Logic synthesis is a plus·Scripting skills (TCL/Perl/Shell) is a mustOther skills:• Experience in leading and managing teams• Good communication skills.Tools: Magma Talus , ICC , SOCe, Apache , PrimeTimeSI, Calibre, Hercules.Professionals interested to explore this opportunity can revert on shilpar@roljobs.com with updated resume and with complete education and employment details.

  • Date Posted:  31-Jul-2012
  • Experience Level:  3 to 12 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area:  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  Bangalore
  • Salary:  Not Specified
  • Job Type:  Permanent

Keywords:Physical design SOC encounter back end design net list to GDS

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100% Match

Physical design Engineer Jobs with 20+ Lakhs Salary

Position : Physical designExperience : 3- 9 yearsLocation : BangaloreQualification : B.E. / B.Tech / M.E. / M.TechDescription :·Successful implementation of multimillion gate SoC designs in 65nm,45nm,28nm technologies·Should be capable of handling block of 1M plus place able instances·Hands on experience in complete Netlist to GDS implementation on high frequency design·Hands-On expertise in flip-chip designs·Work on all aspects of physical design including synthesis, IO ring creation, Bump placement , floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tape out·Expertise in executing hierarchical designs - Floor planning, Partitioning, Budgeting, Integration and Signoff·Expertise in Signoff - STA with Crosstalk and OCV, IR - Static and Dynamic, Physical Verification Closure.·Low Power expertise - UPF/CPF based Floor planning and Optimization·Logic synthesis is a plus·Scripting skills (TCL/Perl/Shell) is a mustOther skills:• Experience in leading and managing teams• Good communication skills.Tools: Magma Talus , ICC , SOCe, Apache , PrimeTimeSI, Calibre, Hercules.Professionals interested to explore this opportunity can revert on shilpar@roljobs.com with updated resume and with complete education and employment details.

  • Date Posted:  31-Jul-2012
  • Experience Level:  3 to 12 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area:  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  Bangalore
  • Salary:  Not Specified
  • Job Type:  Permanent

Keywords:Physical design SOC encounter back end design net list to GDS

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100% Match

Physical design jobs @ Bangalore

Position : Physical designExperience : 3-10 yearsLocation : BangaloreDescription :SoC and Block Level Floor planningExperience in SOC encounter.Netlist to GDS exposure with timing analysis.Timing Closure Multi Mode and Multi Corner Timing ClosureCustom design for critical paths. (Hand design of netlist and hand placement)High-speed DDR interface timing closure.Professional interested to explore this opportunity can revert on shilpar@roljobs.com with updated resume.

  • Date Posted:  09-Mar-2013
  • Experience Level:  3 to 12 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area:  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  Bangalore
  • Salary:  Not Specified
  • Job Type:  Permanent

Keywords:physical design SOC encounter IC compiler floor planning backend design netlist to GDS

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100% Match

Physical Design Jobs @ Bangalore

Physical Design Jobs @ BangaloreClient of Roland & AssociatesSkills : Physical design,SOC encounter,Backend designExperience : 3-10 yearsLocation : BangaloreSoC and Block Level Floor planningExperience in SOC encounter.Netlist to GDS exposure with timing analysis.Professional interested to explore this opportunity can revert on shilpar@roljobs.com with updated resume.

  • Date Posted:  27-Apr-2013
  • Experience Level:  3 to 10 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area:  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  Bangalore
  • Salary:  Not Specified
  • Job Type:  Permanent

Keywords:Physical design SOC encounter Backend design floor planning timing analysis placement and routing IC compiler

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100% Match

Onsite Opportunity for Physical design Professionals

Skill sets: Netlist to GDSII flow ImplementationFloor Planning, Power Planning, Place & Route, Clock Tree Synthesis (CTS)Tapeout experience on 130nm / 90nm / 65nm / 45nm / 32nm / 22nm Designs

  • Date Posted:  02-May-2013
  • Experience Level:  3 to 8 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area:   Not Specified
  • Location:  Malaysia
  • Salary:  Not Specified
  • Job Type:  Permanent

Keywords:Physical design SOC encounter Backend design floor planning timing analysis placement and routing IC compiler

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100% Match

Onsite opportunity - Custom Layout / Memory Layout / IO Layout

Role : Layout Design Engineer (Custom Layout / Library Development / IO Layout)Qualification : B.E/B.Tech /M.Tech/ M.S/ M.E in Electrical or Electronics EnggExperience : 3 -8 YearsLocation : Malaysia (Valid passport is mandatory)Mode : Direct ContractMandatory Skill sets:-Expertise in Block Level & Full Chip Physical Design Verification ( DRC/LVS/RCX)Layout Design of Analog circuits such as Op-Amps, Regulators, ADC, DACLayout Design of IO Cells / AMS etcExpertise in EDA tools for Layout Design :Virtuoso, L-Edit, Assura , Calibre.Tapeout Experience of Medium to Large Complex Analog Designs / LibrariesEmail your updated resume to saku@roljobs.com

  • Date Posted:  04-May-2013
  • Experience Level:  3 to 8 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area:  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  Malaysia
  • Salary:  Not Specified
  • Job Type:  Permanent

Keywords:Physical Design ICC SOC Encounter ICCompiler

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100% Match

Malaysia Jobs - Physical Design Engineer

Job Description :Qualification : B.Tech/M.TechExperience : 3- 8 YearsRole : Project lead / Team Lead / Design Engineers Job Location : Malaysia Mandatory Skill sets Required:Minimum 2 + years of experience in Physical Design.Netlist to GDSII flow ImplementationFloor Planning, Power Planning, Place & Route, Clock Tree Synthesis (CTS)Expertise in EDA tools Cadence SoC Encounter, Synopsys ICC, Magma Blast Fusion / TalusTapeout experience on 130nm / 90nm / 65nm / 45nm / 32nm / 22nm DesignsEmail your Cv to saku@roljobs.com with Current & Expected CTC .

  • Date Posted:  11-May-2013
  • Experience Level:  3 to 8 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area:  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  Malaysia
  • Salary:  800000 - 1500000
  • Job Type:  Permanent

Keywords:Physical Design ICC SOC Encounter ICCompiler

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100% Match

Physical Design Jobs @ Malaysia

Physical Design Jobs @ MalaysiaClient of Roland & AssociatesSkills : Physical design,SOC encounter,Backend design,Netlist to GDSExperience : 3-8 yearsLocation : MalaysiaSoC and Block Level Floor planningExperience in SOC encounter.Netlist to GDS exposure with timing analysis.Professional interested to explore this opportunity can revert on shilpar@roljobs.com with updated resume.

  • Date Posted:  18-May-2013
  • Experience Level:  3 to 8 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area:  Any
  • Location:  Malaysia
  • Salary:  300000 - 2000000
  • Job Type:  Permanent

Keywords:Physical design SOC encounter Backend design Net list to GDS

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