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Physical Design Engineer opening in a Product based MNC @ Greater Noida

Hi, About Client :Product based MNC @ Greater Noida, Client of Roland & Associates. Job Description: Physical design including Synthesis, floorplan, P&R, STA, physical verification and chip finishing. Experience in latest technology e.g. 40nm, 32nm complex (low-power/high speed) block implementation. Tools: Cadence Encounter, Primetime, Calibre Persons should have worked on chip block/top implementation and an attitude of hard-work and willing to go extra mile in dynamically changing environment. Education: >70% in 10th, 12th and high rank in engineering. Qualification: B.Tech / M.Tech Electronics Location : Greater Noida Exp: 2-6 yrs Professionals interested in exploring this opportunity can forward their updated CVs to sowmyag@roljobs.com with following details. Current Ctc: Expected Ctc: Notice Period: Please send references ,if you have. Thanks & Regards, Sowmya.G Roland & Associates - Leaders in Social Media Recruitment E- Mail: sowmyag@roljobs.com Mobile: 08042821634 Bangalore.

  • Date Posted:  16-Apr-2012
  • Experience Level:  2 to 6 yrs
  • Industry:  Telcom/ISP
  • Functional Area:   Not Specified
  • Location:  Bangalore
  • Salary:  Not Specified
  • Job Type:  Permanent

Keywords:Floor plan STA

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Physical Design Engineer opening in a Product based MNC @ Chennai

Hi, About Client : Product based MNC @ Chennai, Client of Roland & Associates. Designation : Physical Design Engineer Job Description: Physical Design: Netlist to GDSII – PnR including STA, SI, Power Analysis, PV targeted to 65nm & below. Tools – Synopsys IC Compiler, PT-SI, Magma-talus & Calibre Experience _ 2 to 8 Years Education: B.E/BTech M.E/MTech Professionals interested in exploring this opportunity can forward their updated CVs to apoorv@roljobs.com with following details. Current Ctc: Expected Ctc: Notice Period: Please send references ,if you have. Thanks & Regards, Apoorv Shrivastava Roland & Associates - Leaders in Social Media Recruitment E- Mail: apoorv@roljobs.com Mobile: 08042821635

  • Date Posted:  17-Apr-2012
  • Experience Level:  2 to 8 yrs
  • Industry:  IT-Software/Software Services
  • Functional Area :  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  Chennai
  • Salary:  Not Specified
  • Job Type:  Permanent
100% Match

Physical Design Engineer opening in a Product based MNC @ Chennai

Hi, About Client : Product based MNC @ Chennai, Client of Roland & Associates. Designation : Physical Design Engineer Job Description: Physical Design: Netlist to GDSII – PnR including STA, SI, Power Analysis, PV targeted to 65nm & below. Tools – Synopsys IC Compiler, PT-SI, Magma-talus & Calibre Experience _ 2 to 8 Years Education: B.E/BTech M.E/MTech Professionals interested in exploring this opportunity can forward their updated CVs to tulika@roljobs.com with following details. Current Ctc: Expected Ctc: Notice Period: Please send references ,if you have. Thanks & Regards, Apoorv Shrivastava Roland & Associates - Leaders in Social Media Recruitment E- Mail: apoorv@roljobs.com Mobile: 08042821635

  • Date Posted:  17-Apr-2012
  • Experience Level:  2 to 8 yrs
  • Industry:  IT-Software/Software Services
  • Functional Area :  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  Chennai
  • Salary:  Not Specified
  • Job Type:  Permanent
100% Match

Physical Design opening in a Product based MNC @ Chennai

Hi, About Client : Product based MNC @ Chennai, Client of Roland & Associates. Designation : Physical Design Engineer Job Description: Physical Design: Netlist to GDSII – PnR including STA, SI, Power Analysis, PV targeted to 65nm & below. Tools – Synopsys IC Compiler, PT-SI, Magma-talus & Calibre Experience _ 2 to 8 Years Education: B.E/BTech M.E/MTech Professionals interested in exploring this opportunity can forward their updated CVs to tulika@roljobs.com with following details. Current Ctc: Expected Ctc: Notice Period: Please send references ,if you have. Thanks & Regards, Tulika Shrivastava Roland & Associates - Leaders in Social Media Recruitment E- Mail: tulika@roljobs.com Mobile: 08042821638

  • Date Posted:  18-Apr-2012
  • Experience Level:  2 to 8 yrs
  • Industry:  IT-Software/Software Services
  • Functional Area :  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  Chennai
  • Salary:  Not Specified
  • Job Type:  Permanent
100% Match

Physical Design Manager

Location: Hyderabad/Bangalore/VizagExperience: 8-13yearsJob Description:He/She should be able to do top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-biasSkills Required: Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closureExtensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools.Expertise in scripting languages such as PERL, TCLStrong Physical Verification skill set.Static Timing Analysis in Primetime or Primetime-SIIf you are interested mail your updated CV to ashwinikn@roljobs.comShare with people in your network who may be interested

  • Date Posted:  14-Jul-2012
  • Experience Level:  8 to 13 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area :  Engineering Design/R&D
  • Location:  Bangalore
  • Salary:  Not Specified
  • Job Type:  Permanent

Keywords:floor plan STA

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Physical Design Engineer

Expereince:3-7 YearsLocation:USASkills:Physical Design, floor planning, STA, Synthesis, Timing Closure

  • Date Posted:  18-Aug-2012
  • Experience Level:  3 to 7 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area :  IT Product Development
  • Location:  United States
  • Salary:  Not Specified
  • Job Type:  Permanent
100% Match

Front End Design

4-8 years hands-on experience with multiple tape-outs:Person should have thorough knowledge of Synthesis, design constraints, Formality, Hand-off, DFT insertionlow-power design FE challenges and timing analysis.He should know Synopsys, Atrenta and/or Cadence tools for above skills.

  • Date Posted:  31-Jul-2012
  • Experience Level:  4 to 8 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area :  IT Product Development
  • Location:  Noida
  • Salary:  Not Specified
  • Job Type:  Permanent
100% Match

Job for Physical Design Engineer/Lead/Sr.Lead @ Bangalore - Salary is upto 50 Lakhs

There is a opening for Physical Design Engineer/Lead/Sr.Lead for an MNC for Bangalore Location. Year of Experience : 4-12 YearsLocation : BangaloreSkills Required: * Experience using Synopsys ICC, Magma Talus, Cadence Encounter, Mentor Olympus or Atoptech tools* Successful tape out experience of multiple complex chips(10M+ gates) at 65 or 45 nm* Expertise in floor planning,Physical Synthesis, CTS, Routing* Knowledge of low power flow (power gating, multi-Vt, voltage islands, dynamic voltage scaling, body biasing,etc.)* Hands on experience with STA (Primetime), Power analysis (Apache),DRC / LVS (Calibre), Noise analysis (Celtic / PT-SI)* Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)* Circuit level comprehension of time critical paths in the design* Programming experience in tcl, Perl or C NOTE : SALARY WILL NOT BE A CONSTRAINT FOR THE RIGHT CANDIDATE If you are interested for this position send your CV to shradhak@roljobs.com

  • Date Posted:  08-Jun-2013
  • Experience Level:  4 to 12 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area :  Any
  • Location:  Bangalore
  • Salary:  Not Specified
  • Job Type:  Permanent
100% Match

STA Lead @ Bangalore

Job Description:-Role: STA& Synthesis Lead EngineerExperience : 7-10 YearsJob Location: BangaloreResponsibilities & Skills required:Work independently and with teams in the areas of STA closure, clock tree synthesis.Experience in leading full-chip STA closure, defining mode requirements and corners for timing closureChip-level constraint development and constraint validation- pre-layout and post-layoutStrong knowledge of clock tree synthesis, SI analysis, post-layout effects on timing analysisStrong understanding of ECO cycleAbility to collaborate and resolve issues adjoining timing-closure: delay-annotated gate-level-simulation, DFT timing, etc.Tcl/Perl scripting and automationMust have worked in at least five chip tape-outsWilling to handle a small team of engineers.Strong problem-solving skills and teamwork, Self-motivated, excellent verbal and written communicationEmail your resume to saku@roljobs.com

  • Date Posted:  14-Nov-2013
  • Experience Level:  6 to 10 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area :  IT Software-Embedded/EDA/VLSI/ASIC/Chip Design
  • Location:  Bangalore
  • Salary:  1500000 - 3000000
  • Job Type:  Permanent

Keywords:STA Synthesis

100% Match

STA & Synthesis Engineer jobs in Bangalore

STA & Synthesis Engineer Job opportunity in BangaloreJob Description- Job Type: Full-Time positions- Job Role: STA & Synthesis Engineer- Industry: VLSI- Job Location: Bangalore, India- Job-Experience: 2 - 13 years- Graduation: B.Tech- Main Skill-sets: * STA & Synthesis- Salary: Competitive Pay Package!Those who wish to pursue this challenging STA & Synthesis Engineer Job opportunity, please send your updated resume with contact details immediately to maya@roljobs.comContact DetailsName: Maya NairE-Mail: maya@roljobs.comPhone: +91 804 282 1603

  • Date Posted:  20-Jun-2014
  • Experience Level:  2 to 13 yrs
  • Industry:  Semiconductors/Electronics
  • Functional Area :  Engineering Design/R&D
  • Location:  Bangalore
  • Salary:  Not Specified
  • Job Type:  Permanent

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